24#include <simgear/misc/inputvalue.hxx>
267 virtual bool configure( SGPropertyNode& cfg_node,
268 const std::string& cfg_name,
269 SGPropertyNode& prop_root );
275 return cfg_name ==
"time";
301 const std::string& cfg_name,
302 SGPropertyNode& prop_root )
307 if (cfg_name ==
"time") {
308 _time.push_back(
new simgear::Value(prop_root, cfg_node));
318 _t = q ?
_time.get_value() : 0;
354 bool raisingEdge = c && !_clock;
362 if( !raisingEdge )
return false;
387 SGPropertyNode& cfg )
389 for(
int i = 0;
i < cfg.nChildren(); ++
i )
391 SGPropertyNode_ptr child = cfg.getChild(
i);
392 string cname(child->getNameString());
394 if(
configure(*child, cname, prop_root) )
406 const std::string& cfg_name,
407 SGPropertyNode& prop_root )
421 if( cfg_name ==
"type" ) {
422 string type(cfg_node.getStringValue());
428 "unhandled flip-flop type <" << type <<
">"
432 _implementation = (*
componentForge[type])(prop_root, *cfg_node.getParent());
436 if (cfg_name ==
"set"||cfg_name ==
"S") {
437 _input[
"S"] = sgReadCondition(&prop_root, &cfg_node);
441 if (cfg_name ==
"reset" || cfg_name ==
"R" ) {
442 _input[
"R"] = sgReadCondition(&prop_root, &cfg_node);
446 if (cfg_name ==
"J") {
447 _input[
"J"] = sgReadCondition(&prop_root, &cfg_node);
451 if (cfg_name ==
"K") {
452 _input[
"K"] = sgReadCondition(&prop_root, &cfg_node);
456 if (cfg_name ==
"D") {
457 _input[
"D"] = sgReadCondition(&prop_root, &cfg_node);
461 if (cfg_name ==
"clock") {
462 _input[
"clock"] = sgReadCondition(&prop_root, &cfg_node);
466 if (_implementation && _implementation->isConfigProperty(cfg_name)) {
477 if( _implementation == NULL ) {
478 SG_LOG( SG_AUTOPILOT, SG_ALERT,
"No flip-flop implementation for " << subsystemId() << endl );
486 if( _implementation->getState( dt,
_input, q ) && q0 != q ) {
490 cout <<
"updating flip-flop \"" << subsystemId() <<
"\"" << endl;
491 cout <<
"prev. Output:" << q0 << endl;
492 for( InputMap::const_iterator it =
_input.begin(); it !=
_input.end(); ++it )
493 cout <<
"Input \"" << (*it).first <<
"\":" << (*it).second->test() << endl;
494 cout <<
"new Output:" << q << endl;
static ComponentForge componentForge
ClockedFlipFlopImplementation(bool rIsDominant=true)
constructor for a ClockedFlipFlopImplementation
virtual bool getState(double dt, DigitalComponent::InputMap input, bool &q)
evaluates the output state from the input lines.
virtual bool onRaisingEdge(DigitalComponent::InputMap input, bool &q)=0
pure virtual function to be implemented from the implementing class, gets called from the update meth...
bool _debug
debug flag, true if this component should generate some useful output on every iteration
DFlipFlopImplementation(bool rIsDominant=true)
constructor for a DFlipFlopImplementation
virtual bool onRaisingEdge(DigitalComponent::InputMap input, bool &q)
compute the output state according to the logic table on the raising edge of the clock
InputMap _input
Named input "pins".
virtual bool configure(SGPropertyNode &cfg_node, const std::string &cfg_name, SGPropertyNode &prop_root)
Over-rideable hook method to allow derived classes to refine top-level node parsing.
Interface for a flip flop implementation.
virtual bool configure(SGPropertyNode &cfg_node, const std::string &cfg_name, SGPropertyNode &prop_root)
configure this component from a property node.
virtual bool configure(SGPropertyNode &cfg_node, const std::string &cfg_name, SGPropertyNode &prop_root)
Over-rideable hook method to allow derived classes to refine top-level node parsing.
void update(bool firstTime, double dt)
Implementation of the pure virtual function of the Component class.
virtual bool onRaisingEdge(DigitalComponent::InputMap input, bool &q)
compute the output state according to the logic table on the raising edge of the clock
JKFlipFlopImplementation(bool rIsDominant=true)
constructor for a JKFlipFlopImplementation
void set_output(bool value)
virtual bool configure(SGPropertyNode &cfg_node, const std::string &cfg_name, SGPropertyNode &prop_root)
configure this component from a property node.
bool isConfigProperty(const std::string &cfg_name) const override
MonoFlopImplementation(bool rIsDominant=true)
constructor for a MonoFlopImplementation
virtual bool getState(double dt, DigitalComponent::InputMap input, bool &q)
evaluates the output state from the input lines and returns to the stable state after expiry of the i...
virtual bool getState(double dt, DigitalComponent::InputMap input, bool &q)
evaluates the output state from the input lines
RSFlipFlopImplementation(bool rIsDominant=true)
SRFlipFlopImplementation()
TFlipFlopImplementation(bool rIsDominant=true)
constructor for a TFlipFlopImplementation
virtual bool onRaisingEdge(DigitalComponent::InputMap input, bool &q)
compute the output state according to the logic table on the raising edge of the clock
SGSubsystemMgr::Registrant< FlipFlop > registrantFlipFlop