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Implements a D (delay) flip flop. More...
Inherits FGXMLAutopilot::ClockedFlipFlopImplementation.
Public Member Functions | |
DFlipFlopImplementation (bool rIsDominant=true) | |
constructor for a DFlipFlopImplementation | |
virtual bool | onRaisingEdge (DigitalComponent::InputMap input, bool &q) |
compute the output state according to the logic table on the raising edge of the clock | |
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ClockedFlipFlopImplementation (bool rIsDominant=true) | |
constructor for a ClockedFlipFlopImplementation | |
virtual bool | getState (double dt, DigitalComponent::InputMap input, bool &q) |
evaluates the output state from the input lines. | |
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RSFlipFlopImplementation (bool rIsDominant=true) | |
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virtual | ~FlipFlopImplementation () |
bool | configure (SGPropertyNode &prop_root, SGPropertyNode &cfg) |
configure this component from a property node. | |
virtual bool | isConfigProperty (const std::string &cfg_name) const |
Additional Inherited Members | |
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virtual bool | configure (SGPropertyNode &cfg_node, const std::string &cfg_name, SGPropertyNode &prop_root) |
configure this component from a property node. | |
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bool | _rIsDominant |
Implements a D (delay) flip flop.
Definition at line 215 of file flipflop.cxx.
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inline |
constructor for a DFlipFlopImplementation
rIsDominant | boolean flag to signal if RESET shall be dominant (true) or SET shall be dominant (false) |
Definition at line 221 of file flipflop.cxx.
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inlinevirtual |
compute the output state according to the logic table on the raising edge of the clock
input | a map of named input lines |
q | a reference to a boolean variable to receive the output state |
Implements FGXMLAutopilot::ClockedFlipFlopImplementation.
Definition at line 229 of file flipflop.cxx.